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| E2A0039-16-X2 Semiconductor MSM7532 Semiconductor This version: Jan. 1998 MSM7532 Previous version: Nov. 1996 Single Chip MSK Modem with Compandor for Cordless Telephone GENERAL DESCRIPTION The MSM7532 is a baseband device with a modem function and a baseband voice signal processing function for analog cordless telephone. The voice signal transmitter in this IC consists of a high-pass filter, compressor, scrambler, pre-emphasis, limiter, and splatter filter. The voice signal receiver consists of a bandpass filter, a de-scrambler , a de-emphasis, an expander, an electronic volume, and a ceramic receiver driving circuit. The MODEM in this IC transmits and receives MSK (Minimum Shift Keying) modem signals. FEATURES * Built-in ceramic receiver drive amplifiers * The compander input reference level, limiter level, and modem transmit level are easy to be externally adjusted. * Built-in 2-bit electronic volume * A microphone amplifier and an amplifier available for users are built in. * Mode settings using parallel interfaces * Built-in compander dynamic range: 70 dB * Built-in maximum gain limit circuit for expander * The bit rate of MSK modem is switchable between 2400 bps and 1200 bps. * Scrambler and emphasis can be used by serially connecting them or can be used separately with each other. * Three kinds of the reverse frequency of the scrambler are selectable. * The modem receiver functions detect bit synchronous signals and frame synchronous signals. * Four-step power down modes * Built-in crystal oscillation circuit * Wide range of power supply (1.8 V to 5.5 V) * Package: 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name : MSM7532GS-2K) 1/21 Semiconductor BLOCK DIAGRAM CC3P CC3N CC2 CC1 CMPI LIML UAO UAI TVIO TVI - + MICO MICN MICP SD ST BR MODL RAIO RAI - + VDD GND SGO SGI SW7 RBPF DE-SCR SW3 LPF2 SW4 - + PRE BPF SCR SW3 LPF1 SW4 RCLPF SHAPER MOD MIX-LPF MIXER SW8 DEMBPF COMPRESSOR SW1 HPF1 PREEMPHASIS SW2 LIMITER - + SPLATTER FILTER SW6 RCLPF SW5 TAO RD RT FD FPS BIT FDE CSH RCP RCN DEMOD FRAME DET - DEEMPHASIS SW2 HPF2 + - + PDRC SG OSC VOLTAGE REF. CONT EXPANDER SW1 SW9 SW7 VOLUME RCLPF RVO RVBU X1 X2 VREF CPDL PDN BYP EMP RCK2 RCK1 SEC ME RVE TVE CE3P CE3N CE2 CE1 VOL1 VOL2 MSM7532 2/21 Semiconductor MSM7532 PIN CONFIGURATION (TOP VIEW) 53 RCK1 52 RCK2 54 SEC 51 FPS 49 VDD 50 BIT 55 ME 47 RD 45 SD 48 RT 56 ST 44 X2 TVE 1 RVE 2 PDN 3 FDE 4 BYP 5 TVIO 6 TVI 7 MICO 8 MICN 9 MICP 10 CMPI 11 TAO 12 UAI 13 UAO 14 CC3P 15 CC3N 16 CC1 17 CC2 18 VREF 19 MODL 20 (VDD) 21 GND 22 LIML 23 CPDL 24 SGI 25 SGO 26 BR 27 CE3N 28 43 X1 46 FD 42 PDRC 41 RCN 40 RCP 39 RVBU 38 CSH 37 VOL1 36 VOL2 35 RVO 34 RAI 33 RAIO 32 EMP 31 CE1 30 CE2 29 CE3P 56-Pin Plastic QFP Notes: The pin 49 should be used for VDD. The pin 21 should be connected to VDD or opened. 3/21 Semiconductor MSM7532 PIN AND FUNCTIONAL DESCRIPTIONS TVE Transmit voice signal output control pin. Refer to the TAO pin description. RVE Receive voice signal output control pin. Refer to the RVO pin description. PDN Power down control pin. The four-step power down modes are controlled by the PDN, ME, RVE, and TVE pins. PDN RVE TVE ME Processing Section Transmit Modem Receive Modem Oscillation Circuit Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 1 1 1 0 0 0 1 0 1 0 X 0 X X X 1 OFF OFF OFF OFF ON OFF OFF OFF ON ON OFF OFF ON ON ON OFF ON ON ON ON Voice signal Crystal Other than above X: Don't care In Mode 5, all the circuits are ON. The MODEM demodulation circuit and FD pin are reset to zero by setting to Mode 1 or Mode 2 (PDN = "1", RVE = "0"). After turning the power ON, set the LSI into one of these modes, then reset it before using. To hold the voice signal processing section ON during transmission of MSK signals, set the ME and TVE pins to "1". In this case, the input from TVI is not output to TAO. Refer to the TAO pin description. FDE Pin used to control the function of frame synchronous signal detection circuit. If digital "0" is entered in this pin, the FD pin remains reset at "0" level. The RT and RD pins are always active. If digital "1" is entered in this pin, the frame synchronous signal detection circuit becomes active. And the RT and RD pins are fixed at "1" level until the FD pin goes to "1" level by detecting the frame synchronous signals. Refer to Figure 3 "Receive Signal Timing". BYP Compander path selection pin. BYP 0 1 Transmit side Compressor is connected to the path. Compressor is bypassed to the path. Receive side Expander is connected to the path. Expander is bypassed to the path. Note SW1 When the expander is used, the maximum gain of expander is limited to approximately +12 dB. This tendency will appear as the input signal level is increased when VDD is larger (e. g., 5 V) and VCPDL is smaller (e,g., 0.1 V); the input/output characteristics then change automatically from expander characteristics to linear characteristics with constant gain. 4/21 Semiconductor MSM7532 TVI, TVIO Pins used to constitute an RC-active filter on the transmit input side. If input signals have frequency components over 50 kHz, these components are output as aliasing noises from the built-in SCF circuit. In order to remove these noises, insert the first or second order RC-active filter with about 10 kHz cut-off frequency, as shown below. CMPI C5 R9 R11 C7 TVI C6 R10 SGO - + C4 TVIO Compressor VTVI C4, C5 for DC cutoff In the case of fc = 10 kHz, gain : 0 dB R9 = R10 = R11 = 68 kW C5 = 0.22 mF, C6 = 510 pF, C7 = 110 pF Compressor In the case of fc = 10 kHz, gain : 0 dB R32 = R33 = 51 kW C5 = 0.22 mF, C26 = 300 pF 5/21 Semiconductor MSM7532 MICO, MICN, MICP MICN is the microphone amplifier inverting input pin, MICP is the non-inverting input pin, and MICO is the output pin. Only during power down mode 1 or 2, the amplifier is powered down and the MICO potential is undefined. These pins can also be used for applications other than microphone amplifier. VDD Output MICO MICN - + MICP CMPI Input pin to the compressor. Connect this pin to the TVIO pin with a 0.1 mF capacitor in order to prevent the malfunction of the compressor which may occur if DC input offset exists. TAO Transmit analog signal output pin. According to control data on ME and TVE, TAO is set as shown below. ME 0 0 1 TVE 0 1 X TAO No signal output (potential = VSG) Voice signal output (signal from TVI, TVIO) MSK modulator output Note SW6 SW5 X: Don't care UAI, UAO Inverting input pin (UAI) and output pin (UAO) for the amplifier available for users. These pins are used as a gain control amplifier that can match the internal signal level of the LSI with the input level of the radio circuit. The amplifier can drive a resistance over 2 kW. In the power down mode 1 and 2, the amplifier enters power down mode. Since the amplifier uses the power supply for the built-in transmitter, the amplifier should be used to control signals for the transmitter. C28 is a capacitor for oscillation prevention. Be sure to use a capacitor of 20 pF or more. If this amplifier is not used, connect UAI to UAO directly and remove R1, R2, C1, and C28. C1 R1 R2 C28 TAO UAO UAI + - 6/21 Semiconductor MSM7532 CC3P, CC3N Pins used to connect a capacitor for defining a time constant of output transient response for the compressor. Insert a 0.22 mF capacitor between CC3N and CC3P. CC2, CC1 Pins used to connect capacitors for removing DC offset in the compressor. Insert a 0.22 mF capacitor between CC2 and SGO, and between CC1 and SGO. VREF Output pin for internal reference voltage source. The VREF output voltage is VSG +0.5 V. The voltages into which the voltage between VREF pin and SGO pin is divided by the resistors should be supplied to the LIML, MODL, and CPDL pin, respectively. The VREF pin can be directly connected to the LIML pin, MODL pin, or CPDL pin. VREF Limiter MOD Compressor Expander LIML MODL CPDL SGO R4 R6 R8 R3 R5 R7 MODL DC voltage input pin used to define a transmit output level for MODEM. One of the voltages into which the voltage between VREF pin and SGO pin is divided by the resistors should be supplied to this pin. Refer to the VREF description for voltage division by the resistors. If the potential difference between this pin and the SGO pin is VMODL (V), the TAO output level is expressed as follows. VOX = 20 * log (VMODL) + 0.5 (dBV) GND Ground pin (0V). LIML Clamp voltage input pin for deviation limiter. The voice signal maximum RF modulation can be controlled by supplying, to this pin, one of the voltages into which the voltage between VREF pin and SGO pin is divided by the resistors. Refer to the VREF description for voltage division by the resistors. If the potential difference between this pin and the SGO pin is VLIML (V), the limiter level is expressed as follows. VLIML = 20 * log (VLIML) - 3.0 (dBV) 7/21 Semiconductor MSM7532 The DC clamp level is VSG VLIML. LIML + - Inverter From LPF1 Limiter To splatter filter CPDL Input DC voltage reference level definition pin for compander. One of the voltages into which the voltage between VREF pin and SGO pin is divided by the resistors should be supplied to this pin. Refor to the VREF description for voltage division by the resistors. If the potential difference between this pin and the SGO pin is VCPDL, the compressor and expander input reference levels are expressed as follows. VICS = VIES = 20 * log (VCPDL) - 5.8 (dBV) The compressor input reference level and expander input reference level change simultaneously. SGI Built-in signal ground that is reference voltage to be supplied to analog circuit. The DC voltage is one half of the supply voltage. When the power has fewer noises and fewer ripples, the idle noise can be improved by inserting a bypass capacitor over 1 mF between SGI and GND, and between SGI and VDD. If the power has a lot of noises, do not insert a bypass capacitor between SGI and VDD to reduce supply noises. Other capacitors and resistors should be connected to the SGO pin. SGO Signal ground voltage output pin for LSI external circuits. The DC voltage is one half of the supply voltage. Insert a 1 mF capacitor between SGO and GND. To internal circuit SG voltage generation circuit + - SGI VDD C2 C3 SGO C25 BR MODEM data signaling rate switching input. BR 0 1 Data Signaling Rate 1200 bps 2400 bps Note SW8 CE3P, CE3N Pins used to connect a capacitor for defining a time constant of output transient response for the expander. Insert a 0.22 mF capacitor between CE3N and CE3P. 8/21 Semiconductor MSM7532 CE1, CE2 Pins used to connect a capacitor for removing DC offset in the expander. Insert a 0.22 mF capacitor between CE1 and SGO, an 1 mF capacitor between CE2 and SGO. EMP Emphasis path selection pin. EMP 0 1 Transmit side Pre-emphasis circuit is bypassed to the path Pre-emphasis circuit is connected to the path Receive side De-emphasis circuit is bypassed to the path De-emphasis circuit is connected to the path Note SW2 RAIO, RAI Pins used to constitute RC-active filter on the receive signal input side. Refer to the TVIO and TVI description. If the Scrambler circuit is used, using the first order RC-active filter is recommended. In this case, configure the filter so that either R34 or R35, or both of them, is 60 kW or less. C27 C19 R34 R35 RAI - + RAIO VRAI In the case of fc = 10 kHz, gain : 0dB R34 = R35 = 51 kW C19 = 0.22 mF, C27 = 300 pF RVO Receive voice signal output pin. The RVO state is controlled depending on the digital data set to RVE. RVE 0 1 RVO No signal output (voltage = VSG) Output of signals input to RAI and RAIO Note SW7 VOL1, VOL2 Pins used to set up a gain for the electronic volume. The volume at the stage next to expander is controlled by the pins. VOL2 VOL1 Gain 0 0 1 1 1 0 1 0 +6 dB 0 dB -6 dB -12 dB CSH Pin used to connect a capacitor for removing DC offset in shaper of modem receiver. Insert a 1 mF capacitor between this pin and GND. 9/21 Semiconductor MSM7532 RVBU Ceramic receiver amplifier input pin. Refer to the RCN, RCP description. RCP, RCN Ceramic receiver amplifier output pins. R16 Ceramic receiver (Equivalent capacitance : 68 nF) RCP RVBU - + RC LPF RVO C29 R18 R17 - + RCN R19 R16 = R17 = 1.5 kW R18 10 kW C29 is a capacitor for oscillation prevention. Be sure to use a capacitor of 20 pF or more. If no ceramic receiver amplifier is used, RVBU should be directly connected to RCP, RCN be open, and R16 to R19, and C29 be removed. PDRC Pin used to control power down of the ceramic receiver amplifier. If digital "1" is input in this pin, the two ceramic receiver amplifiers are powered down. If the LSI is in power-down mode 1 or 2 (PDN = "1", RVE = "0"), the ceramic receiver amplifiers are powered down even when the PDRC is at "0". X1, X2 Crystal oscillator connection pins. 3.6864 MHz crystal oscillator should be connected. If the load capacitance of the crystal oscillator is 16 pF, insert a 12 pF capacitor between X1 and GND and between X2 and GND. If an external clock is used, with X1 opened, the clock should be input from X2 through a 200 pF capacitor. High-speed CMOS or TTL, etc C21 X2 C22 3.6864 MHz X1 Open X1 3.6864 MHz 200 pF X2 10/21 Semiconductor MSM7532 SD Transmit data input pin. The data on the SD pin is accepted as the modulator input signals in synchronization with the rising edges of ST. ME SD Input ST tMS Modulator Input Data At the start of data transmission, the synchronization with the receive modem is required. Therefore bit synchronous signals (the alternating patterns of "1" and "0") more than 18 bits should be input in SD. If a radio transmission path is better in S/N ratio, the receive section can properly operate with bit synchronous signals more than 11 bits. FD Frame synchronous detection signal output pin. If the contents of received data in the LSI matches the patterns defined by FPS and BIT in a state where FDE is at "1" level, FD holds "1" level. If FDE is at"0" level, FD is fixed at "0" level. FD is also fixed at "0" in power-down mode 1 or 2 (PDN = "1", RVE = "0"). Take the following procedure to detect frame synchronization: (1) Set the synchronous patterns to be detected at BIT and FPS. (2) Drive FDE at "0" level for 1 ms or more, and then at "1" level. FD is reset to "0" and RT and PD are fixed at "1" level. (3) When a frame synchronous signal has been detected, FD is driven at "1" level and RT and RD become active. To ensure detection of frame synchronous signals, lock in PLL of the receive modem. At the beginning of transmission, transmit synchronous patterns after synchronizing with the opposite modem using a bit synchronous signal of 18 bits or more. Refor to "Receiver Signal Timing" in Fig. 3. RD Receive data output pin. Outputs demodulation serial data for receive signals. Since the RD data is output in synchronization with the falling edges of re-generated timing clock pulse RT, it is recommended that the data be latched on the rising edge of RT. If FDE is at "1" level and FD is at "0" level, RD remains set at "1" level. 11/21 Semiconductor MSM7532 RT Receive data timing re-generation clock output pin. Outputs synchronous clock re-generated by built-in PLL. The data from RD and signals from FD are output in synchronization with falling edges of signals from the RT pin. If FDE is at "1" level and FD is at "0" level, RD remains set at "1" level. Refer to "Receive Signal Timing" in Fig. 3. VDD Power supply pin. A bypass capacitor more than 10 mF should be inserted between this pin and GND. BIT Bit synchronous signal detector control input pin. The FD pin goes to "1" level when the BIT pin and FDE pin are at "1" level, and a 4-bit synchronous signal and 16-bit frame synchronous signal are successively detected. The FD pin goes to "1" level when the BIT pin is at "0" level and the FDE pin is at "1" level, and a 16bit frame synchronous signal is detected. Refer to the FPS description. FPS Frame synchronous pattern setup input pin. BIT 0 0 1 1 FPS 0 1 0 1 Detection Pattern 1001 0011 0011 0110 ( = 9336H) 1100 0100 1101 0110 ( = C4D6H) 1010 1001 0011 0011 0110 ( = A9336H) 1010 1100 0100 1101 0110 ( = AC4D6H) Receiver Handset Base station Handset Base station (These synchronous patterns are for Japanese cordless telephones.) RCK1, RCK2, SEC Reverse frequency selection pins of voice scrambler. These pins are also used to select filter and scrambler bypass mode. SEC PCK1 PCK2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reverse freq. 3200 Hz 3291 Hz 3388 Hz Scrambler works De-scrambler circuit works Pre-BPF, SCR and LPF1 are bypassed DEM-BPF output is connected to RVO pin via RC-LPF (for IC test) Transmit side Pre-BPF, SCR and LPF1 are bypassed Pre-BPF and LPF1 are connected but Scrambler circuit (SCR) is bypassed Receive side DE-SCR and LPF2 are bypassed LPF2 is connected but De-scrambler (DE-SCR) is bypassed Note SW4 SW3 SW4 SW9 SW3 SW4 RCK1 RCK2 0 1 1 1 0 1 12/21 Semiconductor MSM7532 ME Pin used to control MSK modulator output. If digital "1" is entered to this pin, MSK modulator output is connected to splatter filter input. Refer to the TAO description. If digital "1" is entered to the ME pin and digital "0" to the PDN, RVE and TVE pins, the voice signal processing system is powered down. Refer to the PDN pin description. ST Transmit data timing clock output pin. Signals on the SD pin are accepted in synchronization with the leading edges of the signals from the ST pin. If ME is at "0" level, ST remains set at "1" level. 13/21 Semiconductor MSM7532 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage *1 Digital Input Voltage *2 Operating Temperature Storage Temperature Symbol VDD VIA VID Top TSTG Condition Ta = 25C Referred to GND -- -- Rating -0.3 to 7 -0.3 to VDD+0.3 -30 to +70 -55 to +150 V Unit C *1: TVI, MICN, MICP, CMPI, UAI, MODL, LIML, CPDL, RAI, RVBU *2: TVE, RVE, PDN, FDE, BYP, BR, EMP, VOL1, VOL2, PDRC, X2, SD, BIT, FPS, RCK1, RCK2, SEC, ME RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Data Signaling Rate Symbol VDD Top Ts Condition Referred to GND -- BR = "0" BR = "1" TVIO, VDD = 2.1 V to 5.5 V RAIO level VDD = 4.5 V to 5.5 V MODL Referred to VSG Min +1.8 -30 -- -- -- -- 0.05 Typ +2.4 +25 1200 2400 -- -- 0.25 Max +5.5 +70 -- -- -6 dBV 0 1 V 3 DD -0.2 1 V 2 DD -0.3 0.5 VDD -0.8 -- -- -- -- -- -- -- 100 100 100 -- MHz ppm W pF pF mF Unit V C bit/sec Analog Signal Input Level VIA VMODL DC Input Range VLIML VCPDL Microphone Amplifier Common Mode Input Voltage Range C2, C3, C13, C15, C25 C10, C11, C12, C14, C16 C4 C20 C21, C22 C28, C29 Frequency Freq, Tolerance Crystal Resonator Temp, Coefficient Equivalent Series Resistance Load Capacitance VIM -- -- -- -- -- -- -- -- -- -- -- LIML CPDL 0.1 0.1 0.85 -- -- -- -- -- 20 -- -100 -100 -- -- 0.25 0.25 -- 1.0 0.22 0.1 10 12 -- 3.6864 -- -- -- 16 V MICN, MICP -- -- -- -- -- -- -- 25 5C -30 to 70C -- -- 14/21 Semiconductor MSM7532 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics Parameter Symbol IDD Power Supply Current *1 IDDS1 IDDS2 IDDS3 IDDS4 Input Leakage Current *2 Input Voltage *2 Output Voltage *3 IIL IIH VIL VIH VOL VOH Condition Normal mode 2.4 V (mode 5) 5.5 V Power Down mode 1 5.5 V Power Down mode 2 Power Down mode 3 2.4 V Power Down mode 4 (VDD = 2.1 V to 5.5 V, Ta = -30 to 70C) Min -- -- -- -- -- -- -5.0 0 0.8VDD 0 VDD-0.1 Typ 10 16 1.0 120 5.3 6.0 -- -- -- -- -- Max 17 33 50 220 9.2 10.5 5.0 0.2VDD VDD 0.1 VDD V Unit mA mA mA mA VIN = 0 V VIN = VDD -- IOL = -20 mA IOH = 20 mA *1: Refer to PDN in the PIN AND FUNCTIONAL DESCRIPTIONS. *2: TVE, RVE, PDN, FDE, BYP, BR, EMP, VOL1, VOL2, PDRC, SD, BIT, FPS, RCK1, RCK2, SEC, ME *3: FD, RD, RT, ST MODEM AC Characteristics Parameter Transmit Carrier Frequency Symbol fM1 fS1 fM2 fS2 Transmit Carrier Level Receive Carrier Level 1200 bps Bit Error Rate 2400 bps BER VOX VIR SD = "1" SD = "0" SD = "1" SD = "0" R5 = R6 VDD = 2.1 V to 5.5 V VDD = 4.5 V to 5.5 V 8 dB S/N values measured at RAIO 10 dB 11 dB 13 dB Number of data bits required for the PLL to be Locked in within the phase difference of 22.5 or less BN Number of data bits required for the PLL to be Locked in within the phase difference of 90 or less Condition BR = "0" ME = "1" BR = "1" ME = "1" (VDD = 2.1 V to 5.5 V, Ta = -30 to 70C) Min 1199 1799 1199 2399 -30 -30 -- -- -- -- -- Typ 1200 1800 1200 2400 -- -- 1 10-3 5 10-5 1 10-3 5 10-5 -- Max 1201 1801 1201 2401 -3 +4 -- -- -- -- 18 bit -- -- 11 -- dBV Hz Unit -12.7 -11.5 -10.3 Number of PLL Lock-in data bits *1 *1: In the case where receive MSK signals are bit synchronous signals (modulated signals with the alternating pattern of "0" and "1") 15/21 Semiconductor Voice Signal Processing Characteristics Parameter Limiter Clamp Level Transmit Output Distortion Receive Output Distortion Transmit Idle Noise Receive Idle Noise Crosstalk (Receive to transmit) (Transmit to receive) Symbol VLIM HDT HDR NIT NIR CTT CTR GT1 GT2 GR1 GR2 fR Common to transmit and receive fIN = 1 kHz BYP = "1" MSM7532 (VDD = 2.1 V to 5.5 V, Ta = -30 to 70C) Condition R3 = R4, VDD = 2.4 V Min -16 -- -- -- -- -- -- -1.5 -1.5 -1.5 -1.5 3197 3288 3385 -- Typ -15 -48 -45 -62 -80 -60 -90 0 0 0 0 3200 3291 3388 -88 Max -14 -40 -38 -52 -- -50 -- +1 +1 +1 +1 3203 3294 3391 -60 dBV -- -110 -- Hz dB dBV Unit dBV dB fIN = 1 kHz, -18 dBV BYP = EMP = "0", R7 = R8 BYP = EMP = "0" R7 = R8 BYP = EMP = "0" fIN = 1 kHz, -15 dBV SEC = "0" SEC = "1" SEC = "0" SEC = "1" 3200 Hz 3291 Hz 3388 Hz Transmit Gain Receive Gain Reverse Frequency of Voice Scrambler Transmit Reverse Frequency Leak Level Receive Reverse Frequency Leak Level Transmit Input Signal Leak Level Receive Input Signal Leak Level LRT LRR No signal input BYP = RCK2 = "0" SEC = RCK1 = "1" R7 = R8 LIT LIR FT1 FT3 fIN = 1 kHz, -15 dBV BYP = RCK2 = "0" SEC = RCK1 = "1", R7 = R8 100 Hz 300 Hz EMP = "1" BYP = "1" SEC = "0" RCK1 = "0" RCK2 = "0" Reference = 1 kHz 2.5 kHz 3 kHz 5 kHz 100 Hz 300 Hz 2.5 kHz 3 kHz 5 kHz -- -- -- +6.5 +7 -- +1.0 +7.5 -9.5 -11.5 -- -55 -55 -28 +8.0 +9 -32 +2.5 +9.0 -8.0 -9.5 -35 -48 -48 -23 -8.5 +9.5 +11 -27 +4.0 +10.5 -6.5 -7.5 -30 dB -12.5 -10.5 Transmit Filter FT25 FT30 FT50 FR1 FR3 Receive Filter FR25 FR30 FR50 16/21 Semiconductor Voice Signal Processing Characteristics (Continued) Parameter Output Resistance Ceramic Receiver Amplifier (RCP, RCN) Output Load Resistance Receiver Equivalent Capacitance Output Level Output Distortion Output Resistance UserAvailable Amplifier (UAO) Output Load Resistance Output Level Output Distortion Ratio Input Reference Level Output Level *1 Attack Time Recovery Time Input Reference Level Maximum Input Level Expander Output Level *1 Attack Time Recovery Time Electronic Volume Gain Symbol ROC RLC CCR VCR HDC ROU RLU VOU HDU VICS GC2 Compressor GC4 GC6 TAT1 TRE1 VIES VIEM1 VIEM2 GE1 GE2 GE25 TAT2 TRE2 GEV1 GEV2 GEV3 fIN = 1 kHz, R7 = R8 -- Distortion Ratio VDD = 2.1 V to 5.5 V -30 dB VDD = 4.5 V to 5.5 V fIN = 1 kHz, -18 dBV fIN = 1 kHz, R7 = R8 -20 dB fIN = 1 kHz, R7 = R8 -40 dB -60 dB Input Level, -34 dBV AE -22 dBV Input Level, -22 dBV AE -34 dBV fIN = 1 kHz, R7 = R8 R7 = R8 VDD = 2.1 V to 5.5 V VDD = 4.5 V to 5.5 V -10 dB -20 dB -25 dB Input Level, -26 dBV AE -20 dBV Input Level, -20 dBV AE -26 dBV VOL1 = VOL2 = "0" Referenced to RVO level at "0" +6 dB -6 dB -12 dB fIN = 1 kHz, Distortion Ratio -30 dB, VDD = 2.4 V fIN = 1 kHz, -18 dBV -- Condition MSM7532 (VDD = 2.1 V to 5.5 V, Ta = -30 to 70C) Min -- 1.35 -- -- -- -- 2 -- -- Typ 40 1.5 68 -- -68 40 -- -- -- Max -- -- 75 -4 -45 -- -- -6 0 Unit W kW nF dBV dB W kW dBV dB dBV dB -- -64 -45 -19.8 -17.8 -15.8 -10.7 -21.2 -- -- -- -- -- -21.5 -42.2 -- -- -- +5.5 -6.5 -10 -20 -30 3.0 16 -- -- -20 -40 -50 3.0 16 +6.0 -6.0 -9.3 -18.8 -- -- -- -15 -12 -18.5 -37.8 -- -- -- +6.5 -5.5 ms -19.8 -17.8 -15.8 dBV dB ms dB -12.5 -12.0 -11.5 *1: 0 dB is defined as the input level and the output level when the standard input level is input. 17/21 Semiconductor Common Characteristics Parameter Input Resistance Output Resistance Symbol RIA ROX RLX1 Output Load Resistance Condition *1 fO 4 kHz, *2 Output Level: less than -12 dBV Output Level: within the range of V01 and V02 VREF, SGO RLX2 = 40 kW*3 VDD = 2.1 V to 5.5 V VDD = 4.5 V to 5.5 V *3 40 12 -- -- 0.45 -- -- -- -- 0.5 MSM7532 (VDD = 2.1 V to 5.5 V, Ta = -30 to 70C) Min -- -- 10 Typ 10 200 -- Max -- -- -- kW Unit MW W RLX2 RLX3 -- -- -6 0 0.55 Analog Signal Output Level VREF Output DC Voltage SG Output DC Potential Analog Output DC Potential V01 V02 VRF VSG VAO dBV With respect to VSG SGO, SGI TAO, RVO VDD/2 VDD/2 VDD/2 -0.1 +0.1 VDD/2 VDD/2 VDD/2 -0.15 +0.15 V *1: On TVI, MICN, MICP, UAI, MODL, LIML, CPDL, RAI, RVBU *2: On TVIO, MICO, TAO, RAIO, RVO *3: When the distortion ratio is less than or equal to -30 dB on TVIO, MICO, TAO, RAIO, RVO Digital Timing Characteristics Parameter Data Setup Time Data Hold Time Receive Data Output (RTAERD, FD) Synchronous Signal Output (MEAEST) Symbol tS tH tD tMS Condition Refer to Fig. 1 Refer to Fig. 2 Refer to SD pin description (VDD = 2.1 V to 5.5 V, Ta = -30 to 70C) Min 1 1 -300 0 Typ -- -- -- -- Max -- -- 300 834 Unit ms ns ms 18/21 Semiconductor MSM7532 TIMING DIAGRAM ST 50% SD tS tH 50% Figure 1 Input Data Timing RT 50% FD, RD tD 50% Figure 2 Output Data Timing FDE RT Internal RD N-2 N-1 N D1 D2 D3 FD RD D1 D2 D3 N-2, N-1, N : Frame synchronous signal Figure 3 Receive Signal Timing 19/21 Semiconductor MSM7532 APPLICATION CIRCUIT Electronic Volume Control Receive Signal Input Receiver Amplifier Power-Down Control R34 C19 Emphasis Selection C14 R35 C15 CE3P CE3N BR SGO VDD SGI CPDL LIML GND MODL VREF CC2 CC1 CC3N C11 C12 C10 C3 C2 R4 R8 R6 C25 MODEM Signaling Rate Swiching R16 Ceramic Receiver R18 R17 R19 RVBU PDRC VOL1 VOL2 RAIO RCN RVO CSH RCP RAI EMP CE1 X1 X2 SD FD RD RT +- VDD BIT FPS C21 Transmit Data Frame Synchronous Detection Output Receive Data Receive Timing Re-generation Clock Power Supply C20 Bit Synchronous Detection Control Synchronous Pattern Setup Input Reverse Frequency Select Scrambler and Bypass Switching MSK Modulator Control Transmit Data Timing Clock CE2 C22 C29 +- C13 C27 C16 R3 R7 R5 RCK2 RCK1 SEC ME MICO MICN MICP CMPI TVIO PDN TVE Frame Synchronous Detection Control Transmit Voice Output Control Receive Voice Output Control Compander Bypass Control R11 R9 Power Down Control C7 C4 TAO UAI UAO Transmit Signal Output C1 C28 R1 BYP RVE ST CC3P FDE TVI R10 R12 C5 R23 Note: An arrow mark ( ) indicates connection to the SGO pin. Microphone VDD R24 C9 R14 C24 C23 C8 R13 C6 R15 R2 20/21 Semiconductor MSM7532 PACKAGE DIMENSIONS (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 21/21 |
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